Preventing drain to body forward bias in a MOS transistor

ABSTRACT

A voltage level shifting circuit (FIG.  4 ) has a plurality of PMOS transistors M 1 , M 2 , M 3  connected in parallel for respectively driving a capacitive load C L  with a selected different voltage level V 1 , V 2  or V 3 . Transistors M 1 , M 2 , M 3  are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V 1 , V 2  or V 3  to charge the load CL. The largest voltage transistor M 3  has its body connected to its source. The lower voltage transistors M 1 , M 2  have their bodies respectively connected to switches S 1 , S 2 , which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V 3  when the transistors are placed in the OFF condition.

This invention relates to MOS transistor circuits, in general; and, inparticular, to apparatus and methods for biasing MOS transistors used insuch circuits.

BACKGROUND OF THE INVENTION

In a metal-oxide semiconductor field-effect transistor (MOSFET), a thindielectric barrier is used to isolate the gate and the channel. Thevoltage applied to the gate induces an electric field across thedielectric barrier to control the free-carrier concentration in thechannel region. Such devices are referred to as insulated-gatefield-effect transistors (IGFETs), or simply as MOS transistors. A.Grebene, Bipolar and MOS Analog Integrated Circuit Design (1984 J. Wiley& Sons) 106. It should be noted that the term MOS applies even thoughthe gate may be a non-metallic conductor, such as a highly dopedpolysilicon.

MOS transistors are classified as P-channel or N-channel devices,depending on the conductivity type of the channel region. In addition,they can also be classified as “enhancement” or “depletion” devices. Ina depletion-type MOSFET, a conducting channel exists under the gate whenno gate voltage is applied. The applied gate voltage controls thecurrent flow between the source and the drain by depleting a part ofthis channel. In an enhancement-type MOS transistor, no conductivechannel exists between the source and the drain at zero applied drainvoltage. As a gate bias of proper polarity is applied and increasedbeyond a threshold value V_(T), a localized inversion layer is formeddirectly below the gate. This inversion layer serves as a conductingchannel between the source and the drain electrodes. If the gate bias isincreased further, the resistivity of the induced channel is reduced,and the current conduction from the source to the drain is enhanced. Idat 106-107.

MOS transistors make good switches because (1) when the device is ON andconducting, there is no inherent dc offset voltage between the sourceand drain, and (2) the control terminal (the gate) is electricallyisolated from the signal path, thus no dc current flows between thecontrol path and the signal path. Id at 303.

Normally, all the active regions of the MOSFET are reverse-biased withrespect to the substrate. Thus, adjacent devices fabricated on the samesubstrate are electrically isolated without requiring separate isolationdiffusions. The bulk of the semiconductor region is normally inactivesince the current flow is confined to a thin surface channel directlybelow the gate. The bulk of the MOS transistor is called the “body” or“back gate” and, for efficient operation, is normally tied to the samepotential as the source. Id at 108. In certain circuits, such as theconventional voltage level shifting circuits discussed below, however,it may be necessary to apply a different potential to the body in orderto maintain the source-body junction in reverse biased condition andprevent a large junction current from flowing inside the transistor.Such current will interfere with normal circuit operation and canpermanently damage the device or circuit.

Thus, for an N-channel MOS (NMOS) transistor the body (or bulk) must bebiased to make it negative with respect to both source and drain, andfor a P-channel MOS (PMOS) transistor the body must be biased to make itpositive with respect to both source and drain. In a depletion device,if the reverse voltage V_(SB)=V_(S)−V_(B) between the body and thesource (and hence the channel) is increased, the depletion region aroundthe channel will become wider. This will increase the minimum gatevoltage V_(G)=V_(T) necessary to maintain the depletion region withoutcreating a conductive channel. In an enhancement device, on the otherhand, increasing the reverse voltage will narrow the enhancement region,raising the voltage V_(G)=V_(T) needed to develop the enhancement regionto create the channel. This dependence of V_(T) on the magnitude of thereverse biasing voltage V_(SB) is known as the “body effect.” Inaddition to increasing the magnitude of the threshold V_(T), anotherundesired result of the body effect is to reduce the devicetransconductance and the output impedance when the device is operated ina cascode configuration. The body effect phenomenon is a majorlimitation of MOS devices operated at V_(S)≠V_(B). See, Id at 268-271;and R. Gregorian, et al., Analog MOS Integrated Circuits for SignalProcessing (1986 J. Wiley & Sons) 77-78.

FIG. 1A illustrates a typical MOS transistor with its substrate bodytied to its source potential. Such arrangement, shown for a PMOStransistor in FIG. 1A, is equivalent to a PN diode connection between adrain and source, as shown in FIG. 1B. A V_(B)=V_(S)connection isusually effective to reverse-bias the PN junction and, because itminimizes the threshold voltage V_(T), results in efficient operationand minimum area requirements (viz. channel length and width) for thedevice. Also, such connections provide relatively uniform resistivityfor variations in applied voltage V+ in multiple MOS transistor layouts.Body-to-source reverse biasing will not, however, work for circuitswherein the MOS device will be subjected to varying voltages, sometimesplacing the drain voltage V_(D) at a forward biasing potential relativeto the source. This is so for a circuit wherein distinct MOS switchesare connected in parallel to drive a capacitive load with a selected oneof a number of different voltages. An example of such a driverarrangement exists in a matrix-addressable flat-panel display columndriver, in which different MOS transistors are used to apply a selectedone of different voltages to a display column, such as for gray scalecontrol of imaging pixels. In such a voltage level shifter arrangement,the requirement for maintaining a reverse bias across the body diodejunction prevents tying the body to the source. This is because anyvoltage applied to the capacitive load, except the lowest one, willforward bias the other body diodes, preventing charge of the load.

This limitation can be seen by examination of the operation of aconventional voltage level shifting circuit shown of FIG. 2, wherein aplurality of PMOS transistors M₁, M₂, M₃ are connected in parallel, forrespectively driving a capacitive load C_(L) with a selected differentvoltage level V₁ (e.g., 5 volts), V₂ (e.g., 10 volts), or V₃ (e.g., 20volts). If a control voltage V_(G)≧V_(T) is applied to place transistorM₁ in the ON condition (with transistor M₂, M₃ in the OFF condition),voltage V₁ (5 volts) will be applied across the load C_(L) and also tothe drains of transistors M₂, M₃. Because the sources of transistors M₂,M₃ are at higher potentials, this does not pose a forward biasingproblem for the PN junctions of M₂, M₃. The voltage differential V_(DS)for M₂ would be V₁−V₂=−5 volts; and for M₃ would be V₁−V₃=−15 volts. So,even with V_(BS)=0, the body diodes of M₂, M₃ would be reverse biased,and the voltage V₁ would be applied to charge the load C_(L). This wouldnot be the case, however, if one of the transistors M₂ or M₃ were placedin the ON condition. If transistor M₂ were ON (with transistors M₁, M₃OFF), the V₂ (10 volts) would be applied to the drains of M₁, M₃. Thiswould leave M₃ with a reverse biased body diode (V_(DSS)=V₂−V₁=−10volts), but would forward bias the body diode of M₁ (V_(DS1)=V₂−V₁=5volts). Thus, current would flow in the body of M₁ for the M₁ OFFcondition, preventing charge-up of load C_(L). For M₃ in the ONcondition (with M₁ and M₂ OFF), both M₁ and M₂ would have forward biasedbody diodes and current flowing through their bodies would preventcharge-up of load C_(L).

To overcome this problem, the bodies or “back gates” of transistors M₁,M₂ connected to lower voltages V₁, V₂ are connected to a voltageV_(B)≧V_(S) in order to maintain the reverse biased condition. Thegreater source-to-body bias V_(SB) will, however, increase the bodyeffect for the transistors M₁, M₂ connected to apply the lower voltagesV₁, V₂, and the gain of those devices will be decreased. Thus, becausethe channel-ON resistance R_(DSON) directly correlates to the gain, inorder to achieve the same target R_(DSON), the MOS structures M₁, M₂with the larger body effects will require more area or “footprint”. So,all MOS switches except the one tied to the largest voltage, must bemade larger to accommodate the larger higher voltage differentials.Higher potential difference between the body and the source will alsodramatically reduce the efficiency of the operation of the device.Moreover, uniformity of the respective resistances R_(DSON) between thedifferent devices will be reduced, giving less control over thesaturation current point, with the risk of putting the power supplyunder greater burden due to transients.

It is, therefore, an object of the present invention to overcome theforward biasing problem in voltage level shifters and other circuitswhich subject MOS devices to different voltage levels, without the needto use larger MOS transistors to compensate for the body effect.

SUMMARY OF THE INVENTION

The invention provides control of the body effect in MOS transistors,without the need to increase their areas, by switching thesource-to-body bias from one voltage to another when the transistor goesbetween channel current flow ON and OFF conditions. In accordance with apreferred embodiment, a MOS transistor used to selectively connect avoltage to a load has its body connected to its source during the ONcondition, and its body connected to another voltage potential tomaintain reverse bias during the OFF condition.

For an illustrative voltage level shifter application, described ingreater detail below, a plurality of MOS transistors are connected inparallel to act as switches for selective connection of respectivedifferent voltage sources to a capacitive load. Auxiliary switches areprovided to connect the body of each main switch, either to its sourcewhen it is in the ON condition or to the highest one of the appliedvoltages when it is in the OFF condition. For a PMOS implementation, thebody is connected to the source and the drain is tied to ground when theswitch is ON, but when the switch is OFF the body and the gate are bothconnected to the highest voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention have been chosen for purposes ofillustration and description, and are shown with reference to theaccompanying drawings, wherein:

FIG. 1A is a schematic view of a MOS transistor with its body connectedto its source;

FIG. 1B is a schematic view of an equivalent circuit to the MOStransistor of FIG. 1A;

FIG. 2 (prior art) is a schematic view of a conventional MOS devicevoltage level shifter circuit;

FIG. 3A is a schematic view of a MOS transistor with switchedsource-to-body bias in accordance with the principles of the invention;

FIG. 3B is a schematic view of an equivalent circuit to the MOStransistor of FIG. 3A;

FIG. 4 is a schematic view of a MOS device voltage level shifter circuitin accordance with an embodiment of the invention;

FIG. 5 is a schematic view of a specific implementation of an auxiliaryswitch for the embodiment of FIG. 4; and

FIGS. 6 and 7 are schematic views of an NMOS configuration of thecircuit of FIGS. 4 and 5.

Throughout the drawings, like elements are referred to by like numerals.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

For simplicity in understanding the principles of the invention, FIG. 3Ashows a simplified schematic rendition of a MOS transistor employingswitching of source-to-body bias in accordance with the invention. Theillustrated embodiment utilizes PMOS transistors of the enhancementtype. However, those skilled in the art to which the invention relateswill appreciate that the same principles apply to NMOS transistors andto MOS transistors of the depletion type, and that the principlesapplied to the shown PMOS enhancement structure can be readily extendedto their NMOS and depletion MOS equivalents.

In FIG. 3A, transistor M is connected in its ON condition, as in FIG.1A, with its drain connected to ground and its body connected to itssource. The equivalent structure is shown in FIG. 3B, wherein the PNjunction between the drain and body is shown as a diode PN connectedbetween the drain and source. This arrangement is satisfactory andprovides efficient operation, so long as the source-to-body connectionV_(SB)=0 maintains a reverse bias for the diode PN. When the transistorM is placed in an OFF condition, however, the reverse bias conditionwill only exist if the voltage V_(D) applied at the drain is less thanthe voltage V_(S) applied at the source, i.e., V_(D) is less than orequal to V₊. As discussed previously (see discussion relating to FIGS.1A, 1B and 2, above), conventional circuits maintain the reverse bias byconnecting the body, not to the source, but always to the highestpotential expected to be seen by the drain. This increases the “bodyeffect”, however, producing inefficient operation and requiring largerdevices. Such drawbacks are avoided in accordance with the invention bythe provision of an auxiliary switch S₁ which switches the bias voltageof the body to a larger voltage V_(MAX) when the transistor M is placedin the OFF condition. Voltage V_(MAX) is equal to or greater than thelargest voltage expected at the drain of transistor M, thereby ensuringthat the body diode of M will be reverse biased during the OFFcondition. In addition to setting the back gate voltage to V_(MAX), thegate (viz. front gate) voltage V_(G) is also set to switch to the samevoltage V_(MAX) to cause the OFF condition. This ensures that the deviceM will have no potential V_(B)−V_(G) across the channel.

Implementation of the circuit of FIG. 2, utilizing the principles of theinvention, is shown in FIG. 4. Here again, a voltage level shiftingcircuit has a plurality of PMOS transistors M₁, M₂, M₃ connected inparallel for respectively driving a capacitive load C_(L) with aselected different voltage level V₁ (e.g., 5 volts), V₂ (e.g., 10volts), or V₃ (e.g., 20 volts). Transistors M₁, M₂, M₃ are controlled sothat one of them is placed in the ON condition, with the others in theOFF condition, to connect one of the voltages V₁, V₂ or V₃ to charge theload C_(L). The largest voltage transistor M₃ has its body connected toits source, to achieve efficiency in the customary way. The lowervoltage transistors M₁, M₂, on the other hand, now have their bodiesrespectively connected to switches S₁, S₂, which connect the bodies tothe sources when the devices are placed in the ON condition and connectthe bodies to the highest voltage V₃ when the devices are in the OFFcondition. The gates of all the devices M₁, M₂, M₃ are connected toapply the ground (0 volts) potential when the device is to be turned ON,and apply the highest voltage V₃ when the device is to be turned OFF.

In operation, when transistor M₃ is turned ON to apply the highestvoltage V₃ across capacitive load C_(L), M₃ has its gate at 0 volts andits body at V₃; M₂ has its gate at V₃ and its body at V₃ (switch S₂ inthe “B” position); and M₁ has its gate at V₃ and its body at V₃ (switchS₁ in the “B” position). M₃ is ON; M₂ is OFF; and M₁ is OFF; so, theload C_(L) is charged with the voltage V₃. To charge the capacitive loadC_(L) with the voltage V₂, M₃ is turned OFF with its gate and body atV₃; M₂ is turned ON with its gate at 0 volts and its body connected toits source by setting the switch S₁ to its “A” position; and M₁ is leftin the OFF position with its gate at V₃ and its body at V₃. To connectthe lowest voltage V₁ to load C_(L), M₃ is turned OFF with its gate atV₃ and its body at V₃; M₂ is turned OFF with its gate at V₃ and its bodyat V₃ (S₂ in the “B” position); and M₁ is turned ON with its gate at 0volts and its body switched to its source (S₁ switched to its “A”position). In this way, for their respective ON conditions, the bodiesof M₃ and M₂ are connected to the lower voltages V₁ or V₂, respectively,so that the MOS structures do not have to be as large. However, whenthose switches are OFF they are connected to V₃, to prevent reversecurrent flow from the higher voltage V₂ or V₃, when the higher voltageV₂ or V₃ is connected to load C_(L). Thus, each device has its body orback gate switched so that it is either connected to the circuit'shighest potential when in the OFF condition, or its most efficientoperating point (tied to its source) when in the ON condition. Byconnecting to the highest potential (i.e., V₃) in the OFF condition,there is assurance that the forward bias condition will never bereached.

A specific implementation of the construction of auxiliary switch S₁ isshown in FIG. 5. The same construction can be used for switch S₂. Theterminal marked V_(IN) is connected as the control input V_(G) to thegate of M₁. The source of M₁is connected to the voltage V₁, and thedrain of M₁ is connected through the load C_(L) to ground. The auxiliaryswitching circuit S₁ (shown within dashed lines) comprises twoadditional PMOS transistors M₄, M₅ connected in cascoded configurationbetween the voltage V₃ and the source of M₁. M₄ is connected with itssource connected to V₃; its gate connected to the output of an inverterIV₁, whose input is connected to the gate of M₁; and its body connectedto its source. M₅ is connected with its source connected to the drain ofM₄; its gate connected to the gate of M₁; its drain connected to thesource of M₁; and its body connected to the source of M₄. The body of M₁is connected to the source of M₅.

In operation, when V_(IN) is connected to ground (0 volts), turning M₁ON, V₃ will be applied to the gate of M₄ (through the inverter IV₁) and0 volts will be applied to the gate of M₅, thereby turning M₄ OFF andturning M₅ ON. This will connect the body of M₁ through M₅ to the sourceof M₁, allowing efficient operation during the ON condition oftransistor M₁. On the other hand, when voltage V₃ is applied at V_(IN)to turn transistor M₁ OFF, the gate of M₄ will be connected to ground (V _(IN)=0 volts) through the inverter IV₁ and the gate of M₅ will beconnected to V_(IN)=V₃. This will turn transistor M₄ ON and transistorM₅ OFF, thereby applying the voltage V₃ through transistor M₄ to thebody of M₁. Thus, when M₁ is OFF, both its gate and body will beconnected to the voltage V₃.

The switching of V₃and V₁ is all done in M₄ and M₅. Those transistorsare, however, drawing very little current because they serve merely toswitch the back gate, not to convey the main current flow to charge loadC_(L). Thus, their relative R_(DSON) resistances or gains are notcritical and they can be made very small, relative to the main switchingtransistors M₁, M₂ and M₃. The inverter IV₁ is normally present in atypical cross-coupled type of shifter that might be used to loadquiescent current (V_(IN) and V _(IN) terminals are both present). Thus,the switching circuits S₁ and S₂ can be implemented simply by adding twosmall MOS structures to switch the back gates, with the advantage thatthe sizes of the M₁, M₂ devices can be greatly reduced when compared toconventional designs like that of FIG. 3.

Also, switching of the back gates gives better control of ON conditionresistances R_(DSON), with consequential better uniformity ofresistance. As a consequence, the construction becomes less processdependent because the body effect variance is eliminated.

FIGS. 6-7 show the equivalent implementation for an NMOS embodiment ofthe same circuit. For the NMOS embodiment, V₃ is at the lowest potential(e.g., 0 volts), V₂ is at the intermediate potential (e.g., 5 volts) andV₁ is at the highest potential (e.g., 10 volts), and the main NMOStransistors M₁, M₂, M₃ are turned ON by a high voltage swing (V_(IN)>10volts) and turned off by a low voltage swing (V_(IN)=0 volts). Here, themain channel transistor M₁ is an NMOS structure with its sourceconnected to V₁, its gate connected to V_(IN) and its drain connectedthrough the load C_(L) to ground. Transistor M₄ is connected to applythe lowest or V₃ potential to the body of M₁ when V_(IN) is low to turntransistor M₁ OFF. Transistor M₅ is connected to apply the M₁ source orV₁ potential to the body of M₁ when V_(IN) is high to turn transistor M₁ON.

Those skilled in the art to which the invention relates will appreciatethat substitutions and modifications can be made to the describedembodiments, without departing from the spirit and scope of theinvention as defined by the claims.

1. A method for preventing a source-to-body forward bias condition of aPN junction between a drain and a body in a MOS transistor, the methodcomprising: applying voltage to the a gate of the MOS transistor toplace the MOS transistor in an ON condition enabling flow of currentbetween the a source and the drain of the MOS transistor, the sourcebeing at a source voltage; connecting the body of the MOS transistor tothe transistor source for the ON condition; applying voltage to the gateof the MOS transistor to place the MOS transistor in an OFF conditionpreventing flow of current between the source and the drain of the MOStransistor; and switching the body of the MOS transistor from the sourceto a voltage different than the transistor source voltage for the OFFcondition; the different voltage acting to place the PN junction betweenthe drain and the body of the MOS transistor in a source-to-body reversebias condition, when keeping the transistor body connected to thetransistor source would place the PN junction between the drain and thebody of the MOS transistor in a source-to-body forward bias condition,wherein the voltage applied to the gate to place the MOS transistor inthe OFF condition is the same as the different voltage.
 2. The method ofclaim 1, wherein the voltage applied to the transistor gate to place thetransistor in the OFF condition is the same as the different voltage. 3.The method of claim 1, wherein the MOS transistor is a PMOS transistorwith its source connected to a first reference voltage and its drainconnected to ground through a load; and wherein in the OFF condition thetransistor drain is switched to a second reference voltage greater thanthe first reference voltage.
 4. The method of claim 3, wherein thedifferent voltage is the same as the second reference voltage.
 5. Themethod of claim 4, wherein the voltage applied to the transistor gate toplace the MOS transistor in the OFF condition is the same as the secondreference voltage.
 6. A method for preventing a forward source-to-bodybias condition in a PN junction between a drain and a body of a MOStransistor in a circuit having a plurality of MOS transistors connectedin parallel and respectively to a corresponding plurality of referencevoltages, the method comprising: applying voltage to the a gate of afirst one of the plurality of MOS transistors to place the first MOStransistor in an ON condition enabling flow of current between the asource and a drain of the first MOS transistor to apply a first one ofthe plurality of reference voltages to a load, the source of the firstMOS transistor being at the first one of the plurality of referencevoltages; connecting the a body of the first MOS transistor to the firsttransistor source for the ON condition; applying voltage to the gate ofthe first MOS transistor to place the first MOS transistor in an OFFcondition preventing flow of current between the source and the drain ofthe first MOS transistor; applying voltage to the a gate of a second oneof the plurality of MOS transistors to place the second MOS transistorin an ON condition enabling flow of current between the a source and adrain of the second MOS transistor to apply a second one of theplurality of reference voltages to the load and to the drain of thefirst MOS transistor; and switching the body of the first MOS transistorfrom the first transistor source to a voltage different than the firstone of the plurality of reference voltage voltages for the second MOStransistor ON condition; the different voltage acting to place a PNjunction between the drain and the body of the first MOS transistor inthe a reverse bias condition, when keeping the first MOS transistor bodyconnected to the first MOS transistor source would place the PN junctionbetween the drain and the body of the first MOS transistor in asource-to-body forward bias condition.
 7. A voltage level shiftingcircuit, comprising: a plurality of MOS transistors connected inparallel to act as main switches for selective connection of respectivedifferent reference voltage sources to a capacitive load; auxiliaryswitches provided to connect the a body of each main switch, either toits source when that main switch is in the an ON condition or to the ahighest one of the reference voltage sources when that main switch is inthe an OFF condition.